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Neuromorphic Cognitive Systems Institute of Neuroinformatics University of Zurich and ETH Zurich Winterthurerstrasse 190 8057 Zurich Tel. +41 44 635 30 24 Fax +41 44 635 30 53 giacomo@ethz.ch |
We are investigating the computational properties of spike-based neural circuits using theoretical models, software simulation tools, and neuromorphic VLSI circuits and systems. In particular we are interested in soft Winner-Take-All networks, cooperative-competitive networks, spike-based plasticity mechanisms, selective attention mechanisms, vision sensors, and their implementation in VLSI technology.
1 Professor, 2 Post-doctoral fellows, 11 PhD students
The neuromorphic approach implements the principles of computation used by the nervous systems in analog/digital VLSI technology, exploiting the device physics of transistors to reproduce the biophysics of neural cells.
Neuromorphic VLSI devices model the properties of biological systems down to the single neuron and synapse dynamics and use a digital asynchronous communication infrastructure to transmit spikes across chips and to computers and robots.
We are currently investigating spike-based learning algorithms and VLSI circuits for real-time classification of sensory data (such as speech, or visual stimuli), implementing selective-attention architectures and vision sensors for active vision systems, and investigating auditory scene analysis using neuromorphic multi-chip systems.
We plan to develop large-scale, distributed, multi-chip VLSI networks of biologically realistic neural networks, with adaptation and learning.
These multi-chip systems will be used to explore the computational properties of spiking neural circuits, and to implement real-time behaving systems for practical applications.
For analyzing and simulating neural networks we use standard SW tools, ranging from Matlab to Python.
For designing VLSI chips we use the set of Tanner Tools provided via the Europractice Service. VLSI chips are fabricated via both Europractice and MOSIS services. Typically, the VLSI chips are implemented using standard 0.35u CMOS technology, and occupy areas of 10 to 20 square millimeters.
The Telluride Neuromorphic Cognition Engineering Workshop (http://ine-web.org)
The Capo Caccia Workshops toward Cognitive Neuromorphic Engineering (http://cne.ini.uzh.ch)
EU ERC, Swiss National Science Foundation, EU FP7
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